1. Technical Field
Embodiments relate to a semiconductor memory. More particularly, embodiments relate to a write driver circuit for a phase-change memory and a memory including the same.
2. Description of the Related Art
A Phase-change Random Access Memory (PRAM) is a nonvolatile memory device that stores data using a phase-change material, such as GST (Ge—Sb—Te), having a resistance that changes with a phase transition between amorphous and crystalline states. The phase transition may be controlled by controlling a temperature change and the time over which the phase change material is heated and cooled. The PRAM has characteristics of nonvolatility and low power consumption, as well as the advantages of a Dynamic Random Access Memory (DRAM).
Either the crystalline state or the amorphous state of the phase-change material is selected by a level of current flowing through the phase-change material. High current supplied for a short period of time changes the phase-change material into the amorphous state, which is commonly called a RESET state and corresponds to data “1”. A current lower than the RESET current supplied for a long period of time changes the phase-change material into the crystalline state, which is commonly called a SET state and corresponds to data “0”.
The phase-change material has a greater resistance in the RESET state than in the SET state. The memory cell changes from the SET state to the RESET state by heating the phase-change material to a melting temperature or higher through RESET current supply and then fast quenching the phase-change material. On the other hand, the memory cell changes from the RESET state to the SET state by heating the phase-change material to a crystallizing temperature or higher through SET current supply for a predetermined time and then quenching the phase-change material.
In a memory array including a plurality of phase-change memory cells, each memory cell may have different parasitic resistance depending on its layout. Also, loads may differ between signal lines connected to the memory cells. Further, there may be variations due to process margins in the manufacturing process. Accordingly, there may be a difference in RESET current between the memory cells.